%--------------------------------------------------------------------------
 CompactFlash/IDE Interface for the Apple II computer
 Project Home: http://dreher.net/CFforAppleII/
 Project Version 1.2   Feb 8, 2002

 Version 1.2  -  Two or more cards would not work in system at same time
                 because the DBUS245 select logic did not take into account
                 expansion ROM enable flipflop state.
              -  Moved all logic into appleidelogic.tdf file.
 Version 1.1  -  Add 7M clk & DFF to fix IDE drives /IORD & /IOWR timing
 Version 1.0  -  Initial Release

Note: Remember that the Apple II Bus does not have Phase 2!
----------------------------------------------------------------------------%
FUNCTION nandltch (sn, rn) RETURNS (q);
FUNCTION DFF (D, CLK) RETURNS (Q);

SUBDESIGN AppleIDELogic
(
   A0, A1, A2, A3, A8, A9, A10             : INPUT;
   /RW, /DSEL, /IO_STRB, /IO_SEL, 7Mclk    : INPUT;
      
   /R_HOST, R_ATA, W_HOST, /W_ATA          : OUTPUT;
   /IOWR, /IORD, /CS0, /CS1                : OUTPUT;
   /DBUS245, C800_ACT, /EPROM_EN, NOT_RW   : OUTPUT;
   CS_MASK                                 : OUTPUT;
)
VARIABLE
SET_MASK, RESET_MASK, %CS_MASK,% DelayDSEL : NODE;
/CFXX, /C800_FF         : NODE;

BEGIN
   DEFAULTS
       CS_MASK = GND;
       /C800_FF = VCC; 
   END DEFAULTS;


% Expansion Slot ROM enable Flip-flop. Active low signal %
/C800_FF = nandltch(/CFXX, /IO_SEL); 
C800_ACT = !/C800_FF;  % For debug only, can be removed %

% Output for PCB Version 1.2 Revs A & B, chip U2 is wired such that the direction pin 
  needs an inverted version of R/W %
NOT_RW = !/RW;

% EPROM select. Active low signal %
/EPROM_EN = (/C800_FF # /IO_STRB) !$ /IO_SEL;

%------------------------------------------------------------------------------%
% Fix for SanDisk Family of CompactFlash drives. True IDEmode is not quite     %
% True! The idea here is to mask the read cycle the preceeds all write cycles, %
% because the read cycle was confusing the Sandisk                             %

 SET_MASK = /DSEL # (A3 # A2 # A1 # !A0);
 RESET_MASK = /DSEL # (A3 # A2 # !A1 # A0);
 CS_MASK  = nandltch(SET_MASK, RESET_MASK);
%------------------------------------------------------------------------------%

% ------ Delay /IORD and /IOWR approx 50ns using a D type FF and the Apple Bus %
% 7Mhz clock the A0-A3 signals are used to keep from generating these signals  %
% when accessing the latches %

 DelayDSEL = DFF(/DSEL, 7Mclk);
 /IOWR  = /DSEL # DelayDSEL # /RW  # !(A3 # A2 # A1 # A0);
 /IORD  = /DSEL # DelayDSEL # !/RW # !(A3 # A2 # A1 # A0);

% decode address range $CFxx for deselecting the onboard EPROM %
 /CFXX   = !(A8 & A9 & A10 & !/IO_STRB);

% Latch chip select logic %
 /R_HOST  = /DSEL # A3 # A2 # A1 # A0 # !/RW;
  R_ATA   = !/DSEL & (A3 # (A2 & A1)) & /RW;
  W_HOST  = !/DSEL & !(A3 # A2 # A1 # A0) & !/RW;
 /W_ATA   = /DSEL # !(A3 # (A2 & A1)) # /RW;

% device chip select logic % 
 /CS0   = /DSEL # !A3 # (CS_MASK & /RW);
 /CS1   = /DSEL # (A3 # !(A1 & A2)) # (CS_MASK & /RW);
 /DBUS245 = /DSEL & /EPROM_EN & /IO_SEL;

END;